A phase-locked loop (PLL) is commonly used in transceivers. The PLL generates an output signal having a phase related to the phase of an input reference signal. Locking time of the PLL is a specification in the time-division duplex (TDD) applications, such as the time division synchronous (TD-SCDMA) third generation mobile telecommunication (3G), worldwide interoperability for microwave access (WiMAX), etc.
A “blind” condition occurs in a circuit when some input edges of the circuit are close to or overlap each other. As a result, some output edges of the circuit cannot be generated. Alternatively stated, the output edge is missed. In a phase frequency detector (PFD) that has a blind condition, the PLL usually has a longer lock time. In some conditions, such as in high frequency applications of the PLL, the time interval of the reference signal is not much larger than the turn-on pulse used to turn on the charge pump in the PLL. As a result, a blind condition occurs. Decreasing the width of the turn-on pulse does not eliminate the blind condition in all circumstances.
In a synthesizer having a high output frequency, increasing the frequency of the reference signal of the PLL can improve the performance of the phase noise. Increasing the reference frequency, however, increases the chance for the blind condition to occur, which, in many situations, causes a longer lock time or even a failure to lock.
In an approach, a blind condition occurs in the PLL when the end of the period of the reference clock signal is close to the turn-on pulse. As a result, the reset signal of the PFD causes a blind condition. The lock time of the PLL may be longer than expected due to the blind condition.
In another approach, even if there is not a blind condition, the gain of the PFD is not linear during some phase errors. Further, without appropriate circuitry, the circuit to detect the missing clock edge may inaccurately reveal the presence of the missing edge when the phase and the frequency difference between the reference clock and the feedback clock are relatively small.
In another approach, when the phase difference is larger than a predefined value, the blind condition occurs. Additionally, during some phase differences, the gain is flat.
Like reference symbols in the various drawings indicate like elements.